Modifying system routing information in link based systems

ABSTRACT

Methods and apparatus to improve modification of system routing information in link based systems are described. In one embodiment, entries in a first table (storing data corresponding to routing paths between a plurality of components prior to a hot-plug event) and a second table (storing data corresponding to routing paths between the plurality of components after a hot-plug event) may be compared to determine which corresponding routing registers are to be modified in response to the hot-plug event. Other embodiments are also disclosed.

REFERENCE TO RELATED APPLICATION

This application is related to and claims priority from InternationalApplication No. PCT/CN2007/003367 filed on Nov. 29, 2007 and entitled,“MODIFYING SYSTEM ROUTING INFORMATION IN LINK BASED SYSTEMS”; which isentirely incorporated herein by reference for all purposes.

BACKGROUND

The present disclosure generally relates to the field of electronics.More particularly, an embodiment of the invention relates to techniquesfor modifying system routing information in link based systems.

RAS (Reliability, Availability, and Serviceability) has become acritical feature for modern computer system, especially in the serverplatforms. In a link based system, such as CSI (Common SystemInterface), the successful implementation of RAS features such as socket(or link) hot-plug depends on reconfiguration of routing data duringruntime. Generally, routing data regarding immediate neighbors of amember of a link based system may be stored in storage devices local toeach member of the linked based system. Routing data reconfigurationoperations may be handled transparently to the OS (Operation System) byutilizing processing time that would otherwise be used by the OS. Sincethe OS has its own latency requirement, minimizing the routing tablereconfiguration time becomes a key criterion in RAS implementations.

BRIEF DESCRIPTION OF THE DRAWINGS

The detailed description is provided with reference to the accompanyingfigures. In the figures, the left-most digit(s) of a reference numberidentifies the figure in which the reference number first appears. Theuse of the same reference numbers in different figures indicates similaror identical items.

FIGS. 1-2 and 5-8 illustrate block diagrams of embodiments of computingsystems, which may be utilized to implement various embodimentsdiscussed herein.

FIGS. 3-4 illustrate flow diagrams of methods according to someembodiments.

DETAILED DESCRIPTION

In the following description, numerous specific details are set forth inorder to provide a thorough understanding of various embodiments.However, some embodiments may be practiced without the specific details.In other instances, well-known methods, procedures, components, andcircuits have not been described in detail so as not to obscure theparticular embodiments. Various aspects of embodiments of the inventionmay be performed using various means, such as integrated semiconductorcircuits (“hardware”), computer-readable instructions organized into oneor more programs (“software”) or some combination of hardware andsoftware. For the purposes of this disclosure reference to “logic” shallmean either hardware, software, or some combination thereof.

Some of the embodiments discussed herein may allow for more efficientand/or faster change of system routing configuration in a link basedsystem (such as a CSI system), e.g., to improve RAS. More particularly,some techniques enable relatively large computing systems (such as bladeservers having many routes between various nodes which may also bereferred to herein as agents such as discussed with reference to FIG. 1)to more efficiently and/or quickly change system routing configuration,e.g., by reducing the amount of RTA (Routing Table Array) registers thatneed to be computed and updated, for example, during hot-plug eventssuch as during limited time windows available for SMI (System ManagementInterrupt), PMI (Platform Management Interrupt) or other interruptservicing. Also, in an embodiment, system routing configuration may bemodified without changing system topology. Additionally, some of thetechniques discussed herein may be utilized in various types ofcomputing environments, such as those discussed with reference to FIGS.1-8.

More particularly, FIG. 1 illustrates a block diagram of a computingsystem 100, according to an embodiment of the invention. The system 100may include one or more agents 102-1 through 102-M (collectivelyreferred to herein as “agents 102” or more generally “agent 102”). In anembodiment, the agents 102 may be components of a computing system, suchas the computing systems discussed with reference to FIGS. 2-8.

As illustrated in FIG. 1, the agents 102 may communicate via a networkfabric 104. In one embodiment, the network fabric 104 may include acomputer network that allows various agents (such as computing devices)to communicate data. In an embodiment, the network fabric 104 mayinclude one or more interconnects (or interconnection networks) thatcommunicate via a serial (e.g., point-to-point) link and/or a sharedcommunication network. For example, some embodiments may facilitatecomponent debug or validation on links that allow communication withfully buffered dual in-line memory modules (FBD), e.g., where the FBDlink is a serial link for coupling memory modules to a host controllerdevice (such as a processor or memory hub). Debug information may betransmitted from the FBD channel host such that the debug informationmay be observed along the channel by channel traffic trace capture tools(such as one or more logic analyzers).

In one embodiment, the system 100 may support a layered protocol scheme,which may include a physical layer, a link layer, a routing layer, atransport layer, and/or a protocol layer. The fabric 104 may furtherfacilitate transmission of data (e.g., in form of packets) from oneprotocol (e.g., caching processor or caching aware memory controller) toanother protocol for a point-to-point or shared network. Also, in someembodiments, the network fabric 104 may provide communication thatadheres to one or more cache coherent protocols.

Furthermore, as shown by the direction of arrows in FIG. 1, the agents102 may transmit and/or receive data via the network fabric 104. Hence,some agents may utilize a unidirectional link while others may utilize abidirectional link for communication. For instance, one or more agents(such as agent 102-M) may transmit data (e.g., via a unidirectional link106), other agent(s) (such as agent 102-2) may receive data (e.g., via aunidirectional link 108), while some agent(s) (such as agent 102-1) mayboth transmit and receive data (e.g., via a bidirectional link 110).

FIG. 2 illustrates a block diagram of a point-to-point (PtP) computingsystem 200, according to one embodiment of the invention. FIG. 2 showsan example of a CSI link based system with four processors or centralprocessing units (CPUs) (CPU0 through CPU3) and two interface devices202 and 204, which may be implemented as Input/Output Hubs (IOHs) insome embodiments.

In FIG. 2, the illustrated CPUs and interface devices may be CSIcomponents communicating with each other through CSI links (illustratedas bidirectional arrows). Furthermore, the numbers inside each of theboxes or circles that are coupled to the links illustrate sample portnumbers for a given device. As shown in FIG. 2, each of the CPUs may becoupled to a memory subsystem that it is accessible by the respectiveCPU. Alternatively, one or more of the CPUs may share a memory unit (notshown), in addition to or in place of a dedicated memory subsystem. Insome embodiments, the interface devices 202-204 may provide connectivityto I/O devices such as a Peripheral Component Interconnect Express(PCIe) (e.g., complying with PCIe Specification, Revision 2.0, October2006) and/or an I/O Controller Hub (ICH) such as discussed further withreference to FIG. 7. In one embodiment, the processor-to-processorcommunication and/or between the processor and the interface device(s)may be performed using CSI packets. Furthermore, each of the CSIcomponents (e.g., including one or more of the CPUs and/or interfacedevices) may contain a RTA and a Source Address Decoder (SAD). The RTAmay provide the CSI packet routing information to other sockets. The SADmay provide a mechanism to represent routing of the resources such asmemory, I/O, etc.

For the purpose of explaining one embodiment, assume that CPU3 in FIG. 2needs to be removed while the OS is running. In some embodiments, theCSI components support a Quiesce mode by which normal traffic could bepaused during the RTA/SAD change operations. Generally, such eventswhich involve adding, removing, and/or modifying components of acomputing system may be referred to herein as “hot-plug” events. Tohandle the event associated with removing CPU3, the platform maygenerate an SMI to inform the Basic Input Output System (BIOS) that acomponent needs to be removed. In some implementations, the removaloperation after the SMI may involve the following:

1. Select one CPU as the Monarch CPU, which is responsible for executingmost of SMI events handling code. (Below, CPU0 is taken as Monarch CPUfor example);

2. Monarch CPU quiesces the whole system to pause all the traffic goingthrough the CSI links;

3. Monarch CPU computes the new values for the system configuration RTAregisters and updates them;

4. Monarch CPU performs other system configuration operations, e.g.,computing the new values for SAD registers and updating them, disablinglinks to the hot-removed socket, etc.; and

5. Monarch CPU de-quiesces the system and releases the non-monarchprocessors and returns from the SMI. The system continues to run.

In step 3 above, to change system routings, the re-computing routing isperformed by first obtaining the new topology of the routing fabric ofthe socket (or link) being removed. Second, the new values for all RTAregisters may be computed. Finally, all RTA registers are updated. Thisapproach is rather inefficient because it will have to go through allthe RTA registers, computing their values and updating them, even thoughthey preserve the old value after the hot-plug event, e.g., those RTAregisters for routings between CPU0 and CPU1 in the example of FIG. 2.Even worse, for a real system, the RTAs could be a big amount. Forexample, some CPUs may have 12 ports with 80 RTA entries on each portrespectively. So, the process of changing system routings can introducesignificant latency, which in turn increases the system pause timeduring a hot-plug event, even exceeding the OS tolerable deadline in alarger system.

FIGS. 3-4 illustrate flow diagrams of methods 300 and 400, respectively,that may be utilized to more efficiently and/or quickly update routinginformation in a computing system, according to an embodiment. In oneembodiment, various components discussed herein, e.g., with reference toFIGS. 1-2 and 5-8 may be utilized to perform one or more of theoperations discussed with reference to FIG. 3 or 4.

Referring to FIGS. 1-3, at an operation 302, after initiation of ahot-plug event (e.g., as indicated by an interrupt such as an SMI orPMI), new topology of the routing fabric of the socket (or link) beingremoved, added, and/or modified may be obtained, e.g., by reference to asystem level routing table. In one embodiment, an intermediate datatable (which may be referred to herein as a “Routing-Data-Table”) may beused to compute register values for the new routing fabric as well asfilter the changed RTA registers. The cells of the Routing-Data-Tablemay contain the information to route the transactions from a source to adestination.

For example, Table 1 below illustrates an example table corresponding toFIG. 2 before CPU3 is removed. The routing information is computedthrough the routing algorithm, which could be specific or based on thesystem requirement. The example of the Table 1 is computed by theminimal distance algorithm; namely, each cell in the table indicates theminimal routing path from a given source (row) to a give destination(column). However, embodiments of the invention are not limited to theminimal distance algorithm and any routing algorithm may be used withits output adapted to be compliant with the format of theRouting-Data-Table.

TABLE 1 Example of (Current) Routing-Data-Table for Full Connection ToFrom CPU0 CPU1 CPU2 CPU3 IOH0 IOH1 CPU0 n/a 3 1 2 4 1.2 CPU1 1 n/a 2 3 42.3 CPU2 3 2 n/a 1 2.3 4 CPU3 2 1 3 n/a 1.2 4 IOH0 0 1 0.1 0.1 n/a 0.1IOH1 0.1 0.1 0 1 0.1 n/a

Moreover, such routing information may be the intermediate result tocompute the final RTA register value. For a link based system, therouting fabric on each component may be implemented with ports, entries,and virtual channels, etc. So, a number of successive computations maybe performed. Also, depending on the implementation, some or all of therouting table information may be computed at system startup or otherwisebefore you before-hand. Other implementations may compute at least someof the routing table information during a hot-plug event. Furthermore,in some embodiments, the new topology may be obtained by various meansat operation 302, such as based on information provided by a third-partsystem management/assistant agent, being discovered dynamically, etc.

At an operation 304, any necessary modifications may be determined. Forexample, since each cell in the Routing-Data-Table contains the routinginformation from the source to the destination, if a cell value does notchange before and after the hot-plug event, the corresponding RTAregister values will not need to change either; otherwise, RTA registervalues are changed to route the transitions to new ports or paths.

For example, Table 2 below illustrates an example of (New)Routing-Data-Table for CPU3 to be removed from FIG. 2. In an embodiment,at operation 304, by comparing the cell values in theRouting-Data-Tables of the topology before (Table 1) and after thehot-plug event (Table 2), the RTA registers, which need to be computedfurther and updated finally, could be filtered out to increase speedand/or reduce latency associated with a hot-plug event.

TABLE 2 Example of (New) Routing-Data-Table for CPU3 to be Removed ToFrom CPU0 CPU1 CPU2 CPU3 IOH0 IOH1 CPU0 n/a 3 1 n/a 4 1 CPU1 1 n/a 2 n/a4 2 CPU2 3 2 n/a n/a 2.3 4 CPU3 n/a n/a n/a n/a n/a n/a IOH0 0 1  0.1n/a n/a 0.1 IOH1 0 0 0 n/a 0 n/a

For example, by comparing Table 2 with Table 1, it becomes apparent thatremoval of CPU3 results in changes to 6 cells, while 15 cells preservetheir previous values. In some embodiments, the current table may bestored in a different memory device than the new table (e.g., the tablesmay be stored in different memory subsystems or caches discussed withreference to FIG. 2). Alternatively, the tables may be stored in thesame memory device (such a shared memory device or a private memorydevice).

For example, assuming that for each cell time T is needed for thesuccessive computation and hardware updating, then the time spent isreduced from (15+6)T=21T to 6T and it is 3.5 times faster. If oneconsiders the hot-add case (e.g., adding CPU3), then the Table 1corresponds to the Routing-Data-Table after the topology changes, whilethe Table 2 is the original configurations. This is because the cellsfrom and to CPU3 should be counted, so the time spent is reduced from(21+10)T=31T to (6+10)T=16T, which is about 2 times faster. Accordingly,based on the determination made at operation 304, an operation 306computes the new values for the filtered RTA registers. At an operation308, the routing information may be updated based on the computed valuesof operation 306 (e.g., only filtered RTA registers of operation 304 areupdated).

FIG. 4 illustrates a flow diagram of a method 400 that may be used toperform operation 304 of FIG. 3, according to an embodiment. At anoperation 402, new Routing-Data-Table for the new topology may becomputed. In one embodiment, operation 402 may be performed forneighboring components of the component being removed, added, and/ormodified. At an operation 404, the new table may be compared against thecurrent table as discussed with reference to FIG. 3. Based on thecomparison of operation 404, the registers (e.g., RTA registers) thatare to be modified (or filtered) can be determined at operation 406. Atan operation 408, the current routing table may be updated with datafrom the new routing table computed at operation 402.

Because some embodiments may filter only changed RTA registers, assystems increase the number of their components, it becomes apparentthat such embodiments will also result in better returns. For example,in FIG. 5, a relatively large system 500 with 12 processors is shown,where CPU7 (which is in the center of the system) is to be added. Table3 below corresponds to system 500. As can be seen, the number of cellschanged and unchanged are 62 and 70 respectively, so it improves theperformance for (62+70)T to 62T, which is more than 2 times faster.

TABLE 3 Example of CPU7 to be Added Routing Routing To Routing To From(Changed) Count (Unchanged) Count 1 {7, 8} 2 {2, 3, 4, 5, 6, 9, 10, 911, 12} 2 {7, 8, 11} 3 {1, 3, 4, 5, 6, 9, 8 10, 12} 3 {5, 6, 7, 8, 9,10, 11, 8 {1, 2, 4} 3 12} 4 {5, 6, 7, 11} 4 {1, 2, 3, 8, 9, 10, 7 12} 5{7, 8} 2 {1, 2, 3, 4, 6, 9, 10, 9 11, 12} 6 {3, 4, 7, 8, 11, 12} 6 {1,2, 5, 9, 10} 5 7 {1, 2, 3, 4, 5, 6, 8, 9, 11 { } 0 10, 11, 12} 8 {1, 2,3, 5, 6, 7, 9, 10, 9 {4, 12} 2 11} 9 {7, 8} 2 {1, 2, 3, 4, 5, 6, 10, 911, 12} 10  {3, 7, 8} 3 {1, 2, 4, 5, 6, 9, 11, 8 12} 11  {1, 2, 3, 4, 5,6, 7, 8 {9, 10, 12} 3 8} 12  {3, 5, 6, 7} 4 {1, 2, 4, 8, 9, 10, 7 11}Sum — 62 — 70

Further, in system 600 of FIG. 6, a corner CPU (CPU4) is to be removed.Table 4 below corresponds to system 600. For this example, only 3 cellsare change, so the time spent on routing reconfiguration is reduced from(3+107)T to 3T, which is more than 35 times faster.

TABLE 4 Example of CPU4 to be Removed Routing Routing To Routing To from(Changed) Count (Unchanged) Count 1 { } 0 {2, 3, 5, 6, 7, 8, 9, 10, 11,12} 10 2 { } 0 {1, 3, 5, 6, 7, 8, 9, 10, 11, 12} 10 3 {8, 12} 2 {1, 2,5, 6, 7, 9, 10, 11} 8 4 Needn't — Needn't care — care 5 { } 0 {1, 2, 3,6, 7, 8, 9, 10, 11, 12} 10 6 { } 0 {1, 2, 3, 5, 7, 8, 9, 10, 11, 12} 107 { } 0 {1, 2, 3, 5, 6, 8, 9, 10, 11, 12} 10 8 {3} 1 {1, 2, 5, 6, 7, 9,10, 11, 12} 9 9 { } 0 {1, 2, 3, 5, 6, 7, 8, 10, 11, 12} 10 10  { } 0 {1,2, 3, 5, 6, 7, 8, 9, 11, 12} 10 11  { } 0 {1, 2, 3, 5, 6, 7, 8, 9, 10,12} 10 12  { } 0 {1, 2, 3, 5, 6, 7, 8, 9, 10, 11} 10 Sum — 3 — 107

Accordingly, in some embodiments, an intermediate routing data tablewhich contains routing information from a source to a destination may beused. By comparing data tables of before and after a hot-plug event, aminimal set of RTA registers need be computed and update to increaseperformance. Furthermore, even though socket hot-plug events arediscussed herein as examples, embodiments discussed herein also workwell with link hot-plug. The above example uses the SMI to describe theinvention; similar techniques may be used in systems with the PMI.

FIG. 7 illustrates a block diagram of an embodiment of a computingsystem 700. One or more of the components of FIG. 1 and/or FIG. 2 maycomprise one or more components discussed with reference to thecomputing system 700. The computing system 700 may include one or morecentral processing unit(s) (CPUs) 702 (which may be collectivelyreferred to herein as “processors 702” or more generically “processor702”) coupled to an interconnection network (or bus) 704. The processors702 may be any type of processor such as a general purpose processor, anetwork processor (which may process data communicated over a computernetwork 104), etc. (including a reduced instruction set computer (RISC)processor or a complex instruction set computer (CISC)). Moreover, theprocessors 702 may have a single or multiple core design. The processors702 with a multiple core design may integrate different types ofprocessor cores on the same integrated circuit (IC) die. Also, theprocessors 702 with a multiple core design may be implemented assymmetrical or asymmetrical multiprocessors.

The processor 702 may include one or more caches (not shown), which maybe private and/or shared in various embodiments. Generally, a cachestores data corresponding to original data stored elsewhere or computedearlier. To reduce memory access latency, once data is stored in acache, future use may be made by accessing a cached copy rather thanrefetching or recomputing the original data. The cache(s) may be anytype of cache, such a level 1 (L1) cache, a level 2 (L2) cache, a level3 (L-3), a mid-level cache, a last level cache (LLC), etc. to storeelectronic data (e.g., including instructions) that is utilized by oneor more components of the system 700.

A chipset 706 may additionally be coupled to the interconnection network704. Further, the chipset 706 may include a memory control hub (MCH)708. The MCH 708 may include a memory controller 710 that is coupled toa memory 712. In an embodiment, the MCH may also include graphics logicand as a result may be referred to as a graphics MCH (GMCH). The memory712 may store data, e.g., including sequences of instructions that areexecuted by the processor 702, or any other device in communication withcomponents of the computing system 700. In an embodiment, the memory 712may be the same or similar to the memory subsystems shown in FIG. 2.Also, in one embodiment of the invention, the memory 712 may include oneor more volatile storage (or memory) devices such as random accessmemory (RAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), static RAM(SRAM), etc. Nonvolatile memory may also be utilized such as a harddisk. Additional devices may be coupled to the interconnection network704, such as multiple processors and/or multiple system memories.

The MCH 708 may further include a graphics interface 714 coupled to adisplay device 716 (e.g., via a graphics accelerator in an embodiment).In one embodiment, the graphics interface 714 may be coupled to thedisplay device 716 via an accelerated graphics port (AGP). In anembodiment of the invention, the display device 716 (such as a flatpanel display) may be coupled to the graphics interface 714 through, forexample, a signal converter that translates a digital representation ofan image stored in a storage device such as video memory or systemmemory (e.g., memory 712) into display signals that are interpreted anddisplayed by the display 716.

As shown in FIG. 7, a hub interface 718 may couple the MCH 708 to aninput/output control hub (ICH) 720. The ICH 720 may provide an interfaceto input/output (I/O) devices coupled to the computing system 700. TheICH 720 may be coupled to a bus 722 through a peripheral bridge (orcontroller) 724, such as a peripheral component interconnect (PCI)bridge that may be compliant with the PCIe specification, a universalserial bus (USB) controller, etc. The bridge 724 may provide a data pathbetween the processor 702 and peripheral devices. Other types oftopologies may be utilized. Also, multiple buses may be coupled to theICH 720, e.g., through multiple bridges or controllers. For example, thebus 722 may comply with the PCI Local Bus Specification, Revision 7.0,Mar. 9, 7004, available from the PCI Special Interest Group, Portland,Oreg., U.S.A. (hereinafter referred to as a “PCI bus”). Alternatively,the bus 722 may comprise a bus that complies with the PCI-XSpecification Rev. 7.0a, Apr. 73, 7003, (hereinafter referred to as a“PCI-X bus”) and/or PCIe specification, available from the aforesaid PCISpecial Interest Group, Portland, Oreg., U.S.A. Further, the bus 722 maycomprise other types and configurations of bus systems. Moreover, otherperipherals coupled to the ICH 720 may include, in various embodimentsof the invention, integrated drive electronics (IDE) or small computersystem interface (SCSI) hard drive(s), USB port(s), a keyboard, a mouse,parallel port(s), serial port(s), floppy disk drive(s), digital outputsupport (e.g., digital video interface (DVI)), etc.

The bus 722 may be coupled to an audio device 726, one or more diskdrive(s) 728, and a network adapter 730 (which may be a NIC in anembodiment). In one embodiment, the network adapter 730 or other devicescoupled to the bus 722 may communicate with the chipset 706. Otherdevices may be coupled to the bus 722. Also, various components (such asthe network adapter 730) may be coupled to the MCH 708 in someembodiments of the invention. In addition, the processor 702 and the MCH708 may be combined to form a single chip.

Additionally, the computing system 700 may include volatile and/ornonvolatile memory (or storage). For example, nonvolatile memory mayinclude one or more of the following: read-only memory (ROM),programmable ROM (PROM), erasable PROM (EPROM), electrically EPROM(EEPROM), a disk drive (e.g., 728), a floppy disk, a compact disk ROM(CD-ROM), a digital versatile disk (DVD), flash memory, amagneto-optical disk, or other types of nonvolatile machine-readablemedia capable of storing electronic data (e.g., including instructions).

FIG. 8 illustrates a computing system 800 that is arranged in apoint-to-point (PtP) configuration, according to an embodiment of theinvention. In particular, FIG. 8 shows a system where processors,memory, and input/output devices are interconnected by a number ofpoint-to-point interfaces. The operations discussed with reference toFIGS. 1-7 may be performed by one or more components of the system 800.

As illustrated in FIG. 8, the system 800 may include several processors,of which only two, processors 802 and 804 are shown for clarity. Theprocessors 802 and 804 may each include a local memory controller hub(MCH) 806 and 808 to enable communication with memories 810 and 812. Thememories 810 and/or 812 may store various data such as those discussedwith reference to the memory 712 of FIG. 7. As shown in FIG. 8, theprocessors 802 and 804 may also include one or more cache(s) discussedwith reference to FIG. 7.

In an embodiment, the processors 802 and 804 may be one of theprocessors 702 discussed with reference to FIG. 7. The processors 802and 804 may exchange data via a point-to-point (PtP) interface 814 usingPtP interface circuits 816 and 818, respectively. Also, the processors802 and 804 may each exchange data with a chipset 820 via individual PtPinterfaces 822 and 824 using point-to-point interface circuits 826, 828,830, and 832. The chipset 820 may further exchange data with ahigh-performance graphics circuit 834 via a high-performance graphicsinterface 836, e.g., using a PtP interface circuit 837.

In at least one embodiment, one or more operations discussed withreference to FIGS. 1-7 may be performed by the processors 802 or 804and/or other components of the system 800 such as those communicatingvia a bus 840. Other embodiments of the invention, however, may exist inother circuits, logic units, or devices within the system 800 of FIG. 8.Furthermore, other embodiments of the invention may be distributedthroughout several circuits, logic units, or devices illustrated in FIG.8.

Chipset 820 may communicate with the bus 840 using a PtP interfacecircuit 841. The bus 840 may have one or more devices that communicatewith it, such as a bus bridge 842 and I/O devices 843. Via a bus 844,the bus bridge 842 may communicate with other devices such as akeyboard/mouse 845, communication devices 846 (such as modems, networkinterface devices, or other communication devices that may communicatewith the computer network 104), audio I/O device, and/or a data storagedevice 848. The data storage device 848 may store code 849 that may beexecuted by the processors 802 and/or 804.

In various embodiments of the invention, the operations discussedherein, e.g., with reference to FIGS. 1-8, may be implemented ashardware (e.g., circuitry), software, firmware, microcode, orcombinations thereof, which may be provided as a computer programproduct, e.g., including a machine-readable or computer-readable mediumhaving stored thereon instructions (or software procedures) used toprogram a computer to perform a process discussed herein. Also, the term“logic” may include, by way of example, software, hardware, orcombinations of software and hardware. The machine-readable medium mayinclude a storage device such as those discussed herein. Additionally,such computer-readable media may be downloaded as a computer programproduct, wherein the program may be transferred from a remote computer(e.g., a server) to a requesting computer (e.g., a client) by way ofdata signals embodied in a carrier wave or other propagation medium viaa communication link (e.g., a bus, a modem, or a network connection).

Reference in the specification to “one embodiment” or “an embodiment”means that a particular feature, structure, or characteristic describedin connection with the embodiment may be included in at least animplementation. The appearances of the phrase “in one embodiment” invarious places in the specification may or may not be all referring tothe same embodiment.

Also, in the description and claims, the terms “coupled” and“connected,” along with their derivatives, may be used. In someembodiments of the invention, “connected” may be used to indicate thattwo or more elements are in direct physical or electrical contact witheach other. “Coupled” may mean that two or more elements are in directphysical or electrical contact. However, “coupled” may also mean thattwo or more elements may not be in direct contact with each other, butmay still cooperate or interact with each other.

Thus, although embodiments of the invention have been described inlanguage specific to structural features and/or methodological acts, itis to be understood that claimed subject matter may not be limited tothe specific features or acts described. Rather, the specific featuresand acts are disclosed as sample forms of implementing the claimedsubject matter.

What is claimed is:
 1. An apparatus comprising: a storage unit to storea first table corresponding to routing paths between a plurality ofcomponents, coupled via one or more communication links, prior to ahot-plug event and a second table corresponding to routing paths betweenthe plurality of components after the hot-plug event, wherein entries inthe first table are to indicate routing information from each source ofthe plurality of components to each destination of the plurality ofcomponents prior to the hot-plug event, wherein entries in the secondtable are to indicate routing information from each source of theplurality of components to each destination of the plurality ofcomponents after the hot-plug event, wherein the hot-plug event is tocorrespond to an interrupt servicing event; and logic to compare entriesin the first table and the second table to determine which correspondingrouting table array (RTA) registers are to be modified in response tothe hot-plug event, wherein each of the plurality of RTA registers is tostore routing data associated with a respective one of the plurality ofcomponents to indicate packet routing information to the plurality ofthe components, wherein the logic is to cause performance of a removaloperation after occurrence of the interrupt servicing event, wherein theremoval operation is to comprise: pausing of traffic flow through theone or more communication links, perform one or more additionaloperations, and unpausing the traffic flow through the one or morecommunication links.
 2. The apparatus of claim 1, wherein the logic isto cause modification of data stored in the determined RTA registers inaccordance with entries of the second table.
 3. The apparatus of claim2, wherein entries of the second table that are read to modify thedetermined RTA registers store data that is different from data storedin corresponding entries of the first table.
 4. The apparatus of claim1, further comprising a processor that comprises the logic.
 5. Theapparatus of claim 4, wherein the processor comprises one or moreprocessor cores.
 6. The apparatus of claim 1, wherein one or more of theplurality of components, the storage unit, or the logic are on a sameintegrated circuit die.
 7. The apparatus of claim 1, wherein theplurality of components comprise one or more of: one or more processors,one or more interface devices, or one or more memory devices.
 8. Theapparatus of claim 1, wherein the one or more communication linkscomprise one or more point-to-point links.
 9. The apparatus of claim 1,wherein the hot-plug event corresponds to one or more of: adding acomponent, removing a component, or modifying a component of a linkedbased computing system.
 10. The apparatus of claim 1, wherein thestorage unit comprises a first storage device to store the first tableand a second storage device to store the second table.
 11. The apparatusof claim 1, wherein the logic is to compare the entries in the firsttable and the second table, without a need for comparing entries inrouting tables of each of the plurality of components, to determinewhich corresponding RTA registers are to be modified in response to thehot-plug event.
 12. The apparatus of claim 1, wherein the interruptservicing event is to comprise a management interrupt event.
 13. Amethod comprising: determining routing paths between a plurality ofcomponents in a link based computing system in response to occurrence ofa hot-plug event; storing data corresponding to routing paths betweenthe plurality of components after occurrence of the hot-plug event in afirst table, wherein the hot-plug event corresponds to an interruptservicing event; comparing the first table to a second table that storesdata corresponding to routing paths between the plurality of componentsprior to occurrence of the hot-plug event, wherein entries in the firsttable indicate routing information from each source of the plurality ofcomponents to each destination of the plurality of components prior tothe hot-plug event, and entries in the second table indicate routinginformation from each source of the plurality of components to eachdestination of the plurality of components after the hot-plug event; andupdating one or more routing table array (RTA) registers based onresults of the comparing, wherein each of the one or more RTA registersstores routing data associated with a respective one of the plurality ofcomponents to indicate packet routing information to the plurality ofthe components, wherein performance of a removal operation afteroccurrence of the interrupt servicing event comprises: pausing oftraffic flow through one or more communication links, coupled betweenthe plurality of components, performing one or more additionaloperations, and unpausing the traffic flow through the one or morecommunication links.
 14. The method of claim 13, further comprisingdetecting an occurrence of the hot-plug event.
 15. The method of claim13, wherein updating the one or more RTA registers is based on entriesof the first table.
 16. The method of claim 13, further comprisingreplacing data stored in the second table with data stored in the firsttable.
 17. The method of claim 13, wherein the hot-plug eventcorresponds to one or more of: adding a component, removing a component,or modifying a component of a linked based computing system.
 18. Asystem comprising: one or more point-to-point links to couple aplurality of components; a plurality of routing table array (RTA)registers, wherein each of the plurality of RTA registers is to storerouting data associated with a respective one of the plurality ofcomponents to indicate packet routing information to the plurality ofthe components; a storage unit to store a first table corresponding torouting paths between the plurality of components prior to a hot-plugevent and a second table corresponding to routing paths between theplurality of components after the hot-plug event, wherein the hot-plugevent is to correspond to an interrupt servicing event, wherein entriesin the first table are to indicate routing information from each sourceof the plurality of components to each destination of the plurality ofcomponents prior to the hot-plug event, and entries in the second tableare to indicate routing information from each source of the plurality ofcomponents to each destination of the plurality of components after thehot-plug event; and a processor to compute data to be stored in thesecond table in response to occurrence of the hot-plug event and compareentries in the first table and the second table to determine whichcorresponding RTA registers are to be modified in response to thehot-plug event, wherein the processor is to cause performance of aremoval operation after occurrence of the interrupt servicing event,wherein the removal operation is to comprise: pausing of traffic flowthrough the one or more point-to-point links, perform one or moreadditional operations, and unpausing the traffic flow through the one ormore point-to-point links.
 19. The system of claim 18, wherein theprocessor is to cause modification of data stored in the determined RTAregisters in accordance with entries of the second table.
 20. The systemof claim 18, wherein the processor comprises one or more processorcores.
 21. The system of claim 18, wherein one or more of the pluralityof components, the storage unit, or the processor are on a sameintegrated circuit die.
 22. The system of claim 18, wherein theplurality of components comprise one or more of: one or more processors,one or more interface devices, or one or more memory devices.